Static Timing Analysis

Project : HGS_BREW
Build Time : 04/28/16 22:02:31
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 91.979 MHz
Clock_1 CyMASTER_CLK 24.000 MHz 24.000 MHz 72.166 MHz
Clock_2 CyMASTER_CLK 50.000  Hz 50.000  Hz 62.193 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \TFTSHIELD_1:SPIM_1:BSPIM:state_2\/main_8 72.166 MHz 13.857 27.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/clock \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb 3.580
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:tx_status_1\ \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \TFTSHIELD_1:SPIM_1:BSPIM:state_2\/main_8 6.767
macrocell8 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:state_2\ SETUP 3.510
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \TFTSHIELD_1:SPIM_1:BSPIM:state_1\/main_8 72.166 MHz 13.857 27.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/clock \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb 3.580
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:tx_status_1\ \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \TFTSHIELD_1:SPIM_1:BSPIM:state_1\/main_8 6.767
macrocell9 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:state_1\ SETUP 3.510
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_4 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 72.176 MHz 13.855 27.812
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_4 1.940
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_4\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_4 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/main_0 3.126
macrocell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\ \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/main_0 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\ \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/q \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.589
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \TFTSHIELD_1:SPIM_1:BSPIM:RxStsReg\/status_6 73.196 MHz 13.662 28.005
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/clock \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 3.580
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_4\ \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\/main_5 3.897
macrocell4 U(0,3) 1 \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\ \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\/main_5 \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\/q 3.350
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\ \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\/q \TFTSHIELD_1:SPIM_1:BSPIM:RxStsReg\/status_6 2.335
statusicell2 U(0,3) 1 \TFTSHIELD_1:SPIM_1:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_3 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 73.665 MHz 13.575 28.092
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_3 1.940
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_3\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_3 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/main_1 2.846
macrocell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\ \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/main_1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\ \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/q \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.589
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 73.932 MHz 13.526 28.141
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 1.940
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_2\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/main_2 2.797
macrocell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\ \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/main_2 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\ \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/q \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.589
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 73.954 MHz 13.522 28.145
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 1.940
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_1\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/main_3 2.793
macrocell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\ \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/main_3 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\ \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/q \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.589
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 74.856 MHz 13.359 28.308
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 1.940
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_0\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/main_4 2.630
macrocell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\ \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/main_4 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\ \TFTSHIELD_1:SPIM_1:BSPIM:load_rx_data\/q \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.589
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \TFTSHIELD_1:SPIM_1:BSPIM:state_0\/main_3 75.165 MHz 13.304 28.363
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/clock \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb 3.580
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:tx_status_1\ \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \TFTSHIELD_1:SPIM_1:BSPIM:state_0\/main_3 6.214
macrocell10 U(0,5) 1 \TFTSHIELD_1:SPIM_1:BSPIM:state_0\ SETUP 3.510
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_4 \TFTSHIELD_1:SPIM_1:BSPIM:RxStsReg\/status_6 83.056 MHz 12.040 29.627
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_4 1.940
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_4\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_4 \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\/main_0 3.915
macrocell4 U(0,3) 1 \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\ \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\/main_0 \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\/q 3.350
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\ \TFTSHIELD_1:SPIM_1:BSPIM:rx_status_6\/q \TFTSHIELD_1:SPIM_1:BSPIM:RxStsReg\/status_6 2.335
statusicell2 U(0,3) 1 \TFTSHIELD_1:SPIM_1:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 2e+007ns(50  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 62.193 MHz 16.079 19999983.921
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 0.760
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.219
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 5.130
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 4.230
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 67.254 MHz 14.869 19999985.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.290
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.219
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 5.130
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 4.230
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 72.244 MHz 13.842 19999986.158
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 1.210
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.272
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 5.130
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 4.230
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:rstSts:stsreg\/status_0 77.658 MHz 12.877 19999987.123
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 0.760
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:status_tc\/main_1 3.220
macrocell5 U(1,5) 1 \Timer_1:TimerUDB:status_tc\ \Timer_1:TimerUDB:status_tc\/main_1 \Timer_1:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_1:TimerUDB:status_tc\ \Timer_1:TimerUDB:status_tc\/q \Timer_1:TimerUDB:rstSts:stsreg\/status_0 2.307
statusicell3 U(1,5) 1 \Timer_1:TimerUDB:rstSts:stsreg\ SETUP 0.500
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 78.253 MHz 12.779 19999987.221
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 0.760
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.219
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP 6.060
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 78.302 MHz 12.771 19999987.229
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 0.760
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.211
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 6.060
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:rstSts:stsreg\/status_0 85.712 MHz 11.667 19999988.333
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.290
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:status_tc\/main_1 3.220
macrocell5 U(1,5) 1 \Timer_1:TimerUDB:status_tc\ \Timer_1:TimerUDB:status_tc\/main_1 \Timer_1:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_1:TimerUDB:status_tc\ \Timer_1:TimerUDB:status_tc\/q \Timer_1:TimerUDB:rstSts:stsreg\/status_0 2.307
statusicell3 U(1,5) 1 \Timer_1:TimerUDB:rstSts:stsreg\ SETUP 0.500
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 86.438 MHz 11.569 19999988.431
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.290
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.219
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP 6.060
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 86.498 MHz 11.561 19999988.439
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.290
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.211
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 6.060
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:rstSts:stsreg\/status_0 93.870 MHz 10.653 19999989.347
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 1.210
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:status_tc\/main_0 3.286
macrocell5 U(1,5) 1 \Timer_1:TimerUDB:status_tc\ \Timer_1:TimerUDB:status_tc\/main_0 \Timer_1:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_1:TimerUDB:status_tc\ \Timer_1:TimerUDB:status_tc\/q \Timer_1:TimerUDB:rstSts:stsreg\/status_0 2.307
statusicell3 U(1,5) 1 \Timer_1:TimerUDB:rstSts:stsreg\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
miso(0)/fb \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/route_si 91.979 MHz 10.872 30.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P6[6] 1 miso(0) miso(0)/in_clock miso(0)/fb 2.133
Route 1 Net_8614 miso(0)/fb \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/route_si 5.239
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 \TFTSHIELD_1:SPIM_1:BSPIM:state_2\/main_7 3.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 0.620
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_0\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 \TFTSHIELD_1:SPIM_1:BSPIM:state_2\/main_7 2.616
macrocell8 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 \TFTSHIELD_1:SPIM_1:BSPIM:state_1\/main_7 3.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 0.620
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_0\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 \TFTSHIELD_1:SPIM_1:BSPIM:state_1\/main_7 2.616
macrocell9 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 \TFTSHIELD_1:SPIM_1:BSPIM:ld_ident\/main_7 3.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 0.620
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_0\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 \TFTSHIELD_1:SPIM_1:BSPIM:ld_ident\/main_7 2.616
macrocell12 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 Net_8615/main_9 3.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 0.620
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_0\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_0 Net_8615/main_9 2.630
macrocell7 U(0,4) 1 Net_8615 HOLD 0.000
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 \TFTSHIELD_1:SPIM_1:BSPIM:state_2\/main_6 3.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 0.620
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_1\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 \TFTSHIELD_1:SPIM_1:BSPIM:state_2\/main_6 2.789
macrocell8 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 \TFTSHIELD_1:SPIM_1:BSPIM:state_2\/main_5 3.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 0.620
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_2\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 \TFTSHIELD_1:SPIM_1:BSPIM:state_2\/main_5 2.789
macrocell8 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 \TFTSHIELD_1:SPIM_1:BSPIM:state_1\/main_5 3.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 0.620
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_2\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 \TFTSHIELD_1:SPIM_1:BSPIM:state_1\/main_5 2.789
macrocell9 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 \TFTSHIELD_1:SPIM_1:BSPIM:state_1\/main_6 3.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 0.620
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_1\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 \TFTSHIELD_1:SPIM_1:BSPIM:state_1\/main_6 2.789
macrocell9 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 \TFTSHIELD_1:SPIM_1:BSPIM:ld_ident\/main_5 3.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 0.620
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_2\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_2 \TFTSHIELD_1:SPIM_1:BSPIM:ld_ident\/main_5 2.789
macrocell12 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 \TFTSHIELD_1:SPIM_1:BSPIM:ld_ident\/main_6 3.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/clock \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 0.620
Route 1 \TFTSHIELD_1:SPIM_1:BSPIM:count_1\ \TFTSHIELD_1:SPIM_1:BSPIM:BitCounter\/count_1 \TFTSHIELD_1:SPIM_1:BSPIM:ld_ident\/main_6 2.789
macrocell12 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 2.140
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.599
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.239
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_2509/main_0 3.612
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_2509/main_0 3.252
macrocell15 U(1,5) 1 Net_2509 HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.632
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.272
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 5.021
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 1.810
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.211
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 5.029
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 1.810
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.219
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb Net_2509/main_1 5.040
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 1.810
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb Net_2509/main_1 3.230
macrocell15 U(1,5) 1 Net_2509 HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 5.422
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.272
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 1.790
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 5.841
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 0.280
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.350
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.211
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 5.849
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 0.280
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell3 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.350
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.219
datapathcell2 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
miso(0)/fb \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/route_si 7.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P6[6] 1 miso(0) miso(0)/in_clock miso(0)/fb 2.133
Route 1 Net_8614 miso(0)/fb \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\/route_si 5.239
datapathcell1 U(0,4) 1 \TFTSHIELD_1:SPIM_1:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_8610/q ss(0)_PAD 24.554
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,3) 1 Net_8610 Net_8610/clock_0 Net_8610/q 1.250
Route 1 Net_8610 Net_8610/q ss(0)/pin_input 7.084
iocell2 P12[6] 1 ss(0) ss(0)/pin_input ss(0)/pad_out 16.220
Route 1 ss(0)_PAD ss(0)/pad_out ss(0)_PAD 0.000
Clock Clock path delay 0.000
Net_8615/q mosi(0)_PAD 22.692
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,4) 1 Net_8615 Net_8615/clock_0 Net_8615/q 1.250
Route 1 Net_8615 Net_8615/q mosi(0)/pin_input 6.932
iocell7 P6[5] 1 mosi(0) mosi(0)/pin_input mosi(0)/pad_out 14.510
Route 1 mosi(0)_PAD mosi(0)/pad_out mosi(0)_PAD 0.000
Clock Clock path delay 0.000
Net_8616/q sclk(0)_PAD 21.295
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,5) 1 Net_8616 Net_8616/clock_0 Net_8616/q 1.250
Route 1 Net_8616 Net_8616/q sclk(0)/pin_input 5.441
iocell8 P6[7] 1 sclk(0) sclk(0)/pin_input sclk(0)/pad_out 14.604
Route 1 sclk(0)_PAD sclk(0)/pad_out sclk(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
\TFTSHIELD_1:CR_1:Sync:ctrl_reg\/control_1 dc(0)_PAD 23.457
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \TFTSHIELD_1:CR_1:Sync:ctrl_reg\ \TFTSHIELD_1:CR_1:Sync:ctrl_reg\/busclk \TFTSHIELD_1:CR_1:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_8612 \TFTSHIELD_1:CR_1:Sync:ctrl_reg\/control_1 dc(0)/pin_input 6.396
iocell4 P6[3] 1 dc(0) dc(0)/pin_input dc(0)/pad_out 15.011
Route 1 dc(0)_PAD dc(0)/pad_out dc(0)_PAD 0.000
Clock Clock path delay 0.000
\TFTSHIELD_1:CR_1:Sync:ctrl_reg\/control_2 rt_cs(0)_PAD 23.326
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \TFTSHIELD_1:CR_1:Sync:ctrl_reg\ \TFTSHIELD_1:CR_1:Sync:ctrl_reg\/busclk \TFTSHIELD_1:CR_1:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_8613 \TFTSHIELD_1:CR_1:Sync:ctrl_reg\/control_2 rt_cs(0)/pin_input 5.530
iocell5 P6[2] 1 rt_cs(0) rt_cs(0)/pin_input rt_cs(0)/pad_out 15.746
Route 1 rt_cs(0)_PAD rt_cs(0)/pad_out rt_cs(0)_PAD 0.000
Clock Clock path delay 0.000
\TFTSHIELD_1:CR_1:Sync:ctrl_reg\/control_0 cs(0)_PAD 23.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \TFTSHIELD_1:CR_1:Sync:ctrl_reg\ \TFTSHIELD_1:CR_1:Sync:ctrl_reg\/busclk \TFTSHIELD_1:CR_1:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_8611 \TFTSHIELD_1:CR_1:Sync:ctrl_reg\/control_0 cs(0)/pin_input 5.606
iocell3 P6[4] 1 cs(0) cs(0)/pin_input cs(0)/pad_out 15.656
Route 1 cs(0)_PAD cs(0)/pad_out cs(0)_PAD 0.000
Clock Clock path delay 0.000